This invention relates generally to timing or clocking circuitry for use with integrated circuits and more particularly, it relates to a CMOS clock generator for generating internal CMOS phase clock signals having an adjustable overlap voltage.
With the advent of large scale integration (LSI) technology, more and more circuit components are being fabricated onto a single chip of a monolithic integrated circuit so as to yield a higher integration density. Such increased circuit density has resulted in the advantages of reduced assembly cost, higher speed of operation, and low power dissipation. These advantages have motivated logic circuit designers to desire increased number of logic gates to be formed by this LSI technology. When the logic gates are used in the timing and control of the different signals in the operation of digital equipment such as a microprocessor, such logic circuits also require their own clock generator for generating internal phase clock signals for their own use.
Therefore, there has arisen the need of manufacturing a clock generator on the same single semiconductor chip in which the logic gates have a very high density. As the density of the logic gates on the semiconductor chip increases, it becomes a significantly more difficult task to produce perfect semiconductor logic chips. In an effort to improve production yields and logic chip reliability, it is necessary to check the semiconductor logic chips after fabrication to determine whether they operate properly. If the defect is due to the clock generator located on the semiconductor logic chip, it would be desirable to adjust the overlap voltage between the internal phase clock signals in an attempt to repair the defective logic chips.
It would therefore be desirable to provide a CMOS clock generator used with integrated logic circuits for generating internal CMOS phase clock signals in which the overlap voltage is adjustable. The CMOS clock generator of the present invention includes means for adjusting the clock overlap voltage either up or down to speed up or slow down a chip after fabrication. This technique utilizes a laser to break or open up fuses connected to electrodes of transistor devices.